Embedded resilient buffer

ABSTRACT

Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a first input, the first sequential for double sampling the first input; a compare unit to receive an output from the first sequential unit; and a first selection unit controllable by a write pointer of a previous cycle, the first selection unit to receive outputs of each storage unit of the first queue, wherein the first selection unit to generate an output for comparison by the first compare unit.

PRIORITY

The present patent application is a divisional of and incorporates byreference U.S. patent application Ser. No. 13/867,968, titled “EmbeddedResilient Buffer,” filed Apr. 22, 2013.

BACKGROUND

FIFO (First In, First Out) or “Queues” are vital components used forbuffering and flow control in digital designs. A FIFO typically hasstorage (e.g., data-path) and associated read and write pointers(control logic). Low-voltage operation through reduction of minimumvoltage of operation (V_(MIN)) is an effective approach to reduce powerin digital designs. At low supply voltages, logic paths writing to FIFObuffers are susceptible to dynamic variations such as voltage droops ortemperature changes which can lead to timing failures. Tolerance to fasttransients may be needed to maintain robust FIFO buffer operation.

FIG. 1 shows a conventional implementation 100 of a FIFO, enhanced witherror detection sequentials (EDS) at the input to protect FIFO writes,providing dynamic variation tolerance. Implementation 100 consists of amaster-slave flip-flop (MSFF) 101 coupled to a latch 102, an XOR gate103, and a FIFO 104. In this implementation, FIFO 104 is connected inseries to the sampling latch 102 such that output Fifo_in of latch 102is received by FIFO 104. MSFF 101 is used for double sampling of inputdata ‘D.’ The outputs of MSFF 101 and latch 102 are compared by XOR 103to determine whether the outputs differ. If the outputs differ, the XOR103 asserts an Error signal. This conventional implementation 100,however, adds a cycle of latency.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from thedetailed description given below and from the accompanying drawings ofvarious embodiments of the disclosure, which, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1 is a conventional implementation of a First In, First Out (FIFO)with a sequential unit for timing error detection.

FIG. 2 is a queue embedded in parallel with a sampler, according to oneembodiment of the disclosure.

FIG. 3 is a pipeline with queue embedded in parallel with the sampler,and with error detection and recovery, according to one embodiment ofthe disclosure.

FIG. 4 is a detailed description of the pipeline, according to oneembodiment of the disclosure.

FIG. 5 illustrates a timing sequence, according to one embodiment of thedisclosure.

FIG. 6 is a smart device or a computer system or an SoC (system-on-chip)with queue embedded in parallel with the sampler, according to oneembodiment of the disclosure.

DETAILED DESCRIPTION

Interconnection architectures, for example, in a network-on-chip (NoC)of a system-on-chip (SoC), rely on routers to manage messaging trafficbetween nodes (e.g., processor cores, memory). These routers consumepower to operate and may contribute significantly to the overall powerconsumption for a SoC. One strategy for reducing power consumption is toreduce operating voltages. However, at low voltages the routers areprone to dynamic variations such as voltage droops or aging effects,which can potentially lead to timing failures in the router. Robustnessof operation is typically ensured by use of a static voltage guard bandselected at design time. Use of a static voltage guard band requires ahigher operating voltage and increases power consumption. Theembodiments also relate to resilient communication techniques that maybe utilized to provide reliable, efficient communication of messages.

In one embodiment, dynamic variations that manifest as timing failuresin a router are detected using Error Detection Sequential (EDS)mechanisms that can be hardware circuitry. In one embodiment, resilientrouter architecture includes EDS in a processing stage that can operateto protect timing paths within the router. Correction of messagesexposed to timing failures inside the router can be accomplishedutilizing packet replay techniques.

In one embodiment, the EDS scheme provides native protection againstsoft-error (SER) induced events due to double-sampling. In addition, thedisclosed scheme can protect against SER related combinational delaypush-outs and sequential state loss.

In one embodiment, a router (or other component) includes aresiliency-enhanced final stage that operates to protect timing pathswithin the router. For example, a router having EDS mechanisms operatesto protect all timing paths in the router that originates from an output(e.g., FIFO) queue. In one embodiment, correction of packet (or message,or flit) errors based on timing failures within the router (or othercomponent) is accomplished via packet replay techniques.

Because the timing failure at the output stage is determined after amessage has been transmitted to the receiving node (e.g., router,traffic generator), an error signal (e.g., bit, flag, etc.) istransmitted with the message to indicate whether a timing failure hasoccurred, according to one embodiment. Because the error signal may bemeta-stable, it is latched in the input stage of the receiving nodebefore consumption, according to one embodiment. In one embodiment, theerror signal operates as an invalidation signal to cause thecorresponding message to be squashed (or otherwise not consumed or used)by the receiving node.

In one embodiment, the transmitting node (e.g., router) that sufferedfrom the timing failure replays the failed message by rolling back itsstate by the necessary number of clock cycles (e.g., to a checkpoint).In one embodiment, two clock cycles is sufficient. In alternateembodiments, a greater rollback range may be supported. In oneembodiment, this can be accomplished by isolating the control and datapath for the transmitting node and keeping copies for critical data andcontrol state elements (e.g., via flip-flop or latch) in thetransmitting node.

In one embodiment, an output queue (e.g., a FIFO or other type of outputqueue) has enough unused space during normal operation that messagesfrom previous cycles are still present and not overwritten before theyare used for retransmission when necessary. In another embodiment, FIFOdepth can be increased to accommodate additional message space forretransmission. For example, in one embodiment, a timing error isdetermined and the message is retransmitted within two clock cycles. Thetransmitting node is rolled back to a previous state and the failingmessage is retransmitted to the receiving node.

In one embodiment, use of positive phase latches in the EDS mechanismmay cause the output stage prone to hold time failures. This can beavoided by selectively buffering minimum-delay timing paths toEDS-enhanced stages and feeding a pulsed clock to the output stage. Inone embodiment, the output stage receives a configurable pulse widthclock signal and other stages receive a 50% duty cycle clock signal. Inone embodiment, to reduce the effect of within-die and intra-dievariations at very low operating voltages (e.g., near transistorthreshold voltage), a pruned standard cell library with upsizedsequential and combinational logic states may be used.

The embodiments describe a storage queue with an embedded parallelscheme to enable resilient operation with virtually little or no latencyimpact. The combination of error detection and recovery circuits withdynamic adaptation enables processors to adapt to operating environment.The embodiments may also protect circuits from malicious attack. Forexample, if a malicious attack is an errant power virus that results intransient variations (e.g., supply voltage droops, temperature changes,etc.) the embodiments discussed can detect and correct timing errors andimprove design robustness.

In the following description, numerous details are discussed to providea more thorough explanation of embodiments of the present disclosure. Itwill be apparent, however, to one skilled in the art, that embodimentsof the present disclosure may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, in order to avoidobscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals arerepresented with lines. Some lines may be thicker, to indicate moreconstituent signal paths, and/or have arrows at one or more ends, toindicate primary information flow direction. Such indications are notintended to be limiting. Rather, the lines are used in connection withone or more exemplary embodiments to facilitate easier understanding ofa circuit or a logical unit. Any represented signal, as dictated bydesign needs or preferences, may actually comprise one or more signalsthat may travel in either direction and may be implemented with anysuitable type of signal scheme.

Throughout the specification, and in the claims, the term “connected”means a direct electrical connection between the things that areconnected, without any intermediary devices. The term “coupled” meanseither a direct electrical connection between the things that areconnected or an indirect connection through one or more passive oractive intermediary devices. The term “circuit” means one or morepassive and/or active components that are arranged to cooperate with oneanother to provide a desired function. The term “signal” means at leastone current signal, voltage signal or data/clock signal. The meaning of“a,” “an,” and “the” include plural references. The meaning of “in”includes “in” and “on.”

The term “scaling” generally refers to converting a design (schematicand layout) from one process technology to another process technology.The term “scaling” generally also refers to downsizing layout anddevices within the same technology node. The terms “substantially,”“close,” “approximately,” “near,” “about,” etc., generally refer tobeing within +/−20% of a target value.

Unless otherwise specified the use of the ordinal adjectives “first,”“second,” and “third,” etc., to describe a common object, merelyindicate that different instances of like objects are being referred to,and are not intended to imply that the objects so described must be in agiven sequence, either temporally, spatially, in ranking or in any othermanner.

For purposes of the embodiments, the transistors are metal oxidesemiconductor (MOS) transistors, which include drain, source, gate, andbulk terminals. The transistors also include Tri-Gate and FinFettransistors. Source and drain terminals may be identical terminals andare interchangeably used herein. Those skilled in the art willappreciate that other transistors, for example, Bi-polar junctiontransistors—BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used withoutdeparting from the scope of the disclosure. The term “MN” indicates ann-type transistor (e.g., NMOS, NPN BJT, etc.) and the term “MP”indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

FIG. 2 is a circuit 200 of a queue embedded in parallel with a sampler,according to one embodiment of the disclosure. It is pointed out thatthose elements of FIG. 2 having the same reference numbers (or names) asthe elements of any other figure can operate or function in any mannersimilar to that described, but are not limited to such.

In one embodiment, circuit 200 comprises a sequential unit 201, a queue202, and a compare unit 203. In one embodiment, sequential unit 201 isused for sampling input data ‘D’ which is also received by queue 202. Inone embodiment, sequential unit 201 is used for double sampling theinput data ‘D.’ In one embodiment, sequential unit 201 is a flip-flop.In other embodiments, other edge triggered or level sensitive sequentialunits may be used for sequential unit 201.

In one embodiment, queue 202 is a FIFO queue which receives input ‘D’and generates an output “Queue out” after a predefined number of clock(CLK) cycles. In one embodiment, queue 202 comprises series coupled SRAMcells (Static Random Access Memory). In one embodiment, queue 202comprises a shift-register chain. In one embodiment, queue 202 comprisesa chain of flip-flops and/or latches. In other embodiments, otherstorage (and/or sequential) units may be used for form queue 202. In oneembodiment, length of queue 202 is at least three storage units. Forexample, if queue 202 is a FIFO, then the FIFO has three storage unitscoupled together in series.

In one embodiment, output 204 of sequential unit 201 and output 205 ofqueue 202 is compared by compare unit 203. In one embodiment, output ofcompare unit 203 is an ERROR signal. In one embodiment, compare unit 203comprises an XOR logic gate. In other embodiments, other circuits may beused to compare outputs 204 and 205 to generate the ERROR signal. Theembodiment of FIG. 2 forms an embedded resilient buffer or sequential(EDS) which is faster than the EDS of FIG. 1, and its parallelarchitecture allows for resilient operation with virtually no (orsubstantially zero) latency impact.

FIG. 3 is a pipeline 300 with queue embedded in parallel with thesampler, and with error detection and recovery, according to oneembodiment of the disclosure. It is pointed out that those elements ofFIG. 3 having the same reference numbers (or names) as the elements ofany other figure can operate or function in any manner similar to thatdescribed, but are not limited to such.

In one embodiment, pipeline 300 comprises first EDS 301, second EDS 302,data-path logic 303, and replay logic 304. In one embodiment, first andsecond EDS s (301 and 302) have the same architecture of 200 shown inFIG. 2. While FIG. 2 shows a high level design of an EDS, furtherdetails of the EDS architecture are discussed with reference to FIGS.4-5.

Referring back to FIG. 3, in one embodiment, first EDS 301 receivesinput data 305 a and generates a sampled output 305 b which is receivedby data-path logic 303 (e.g., combinational logic). In one embodiment,output 305 c of data-path logic 303 is received by second EDS 302 whichgenerates another sampled output 305 d, where sampled output 305 d issampled off of 305 c. In one embodiment, ERROR signal (same as 306) fromsecond EDS 302 is received by replay logic 304 that generates anadjusted read pointer signal 307 to cause first EDS 301 to resend data305 b for sampling again by second EDS 302.

FIG. 4 is a detailed circuit 400 of the pipeline 300, according to oneembodiment of the disclosure. It is pointed out that those elements ofFIG. 4 having the same reference numbers (or names) as the elements ofany other figure can operate or function in any manner similar to thatdescribed, but are not limited to such.

In one embodiment, circuit 400 is a pipeline comprising first EDS 401,second EDS 402 and data-path 303. So as not to obscure the embodiment ofFIG. 4, pertinent components of each EDS is shown and associated logic.In one embodiment, both first and second EDS (401 and 402) have the samearchitecture i.e., same circuit components.

In one embodiment, first EDS 401 comprises a first queue 401 a (e.g.,FIFO, shift-register chain, chain of SRAMs, etc.) which receives input305 a and generates an output 305 b. In one embodiment, first queue 401a receives a read pointer 307 that points to the storage unit (fromamong a plurality of storage units of queue 401 a) from which data isbeing read and sent out as 305 b. In one embodiment, read pointer 307 isupdated by replay logic 304. While the embodiment of FIG. 4 shows replaylogic 304 to be part of first EDS 401, replay logic 304 may resideoutside the boundary of first EDS 401.

In one embodiment, second EDS 402 comprises first queue 402 a (e.g.,FIFO, shift-register chain, chain of SRAMs, etc.) which receives input305 c from data-path logic 303. In one embodiment, second EDS 402comprises an edge triggered sequential unit (FF1) 402 b (also referredas first sequential unit) which is coupled to first queue 402 a inparallel such that both receive the same input 305 c. In one embodiment,second EDS 402 comprises a first selection unit 402 c which is operable(via select signal) to select one of the outputs of the storage units offirst queue 402 a. In one embodiment, first selection unit 402 c is amultiplexer (M2) which provides output for compare unit 402 d.

In one embodiment, write-pointer (Wr Ptr) logic 402 i generates theselect signal for first selection unit 402 c. In one embodiment,write-pointer logic 402 i tracks write operation to first queue 402 a.For example, write-pointer logic 402 i tracks previous cycle (T−1, where‘T’ is the current time) and controls first selection unit 402 c toselect the exact data in first queue 402 a written in cycle (T−1).

In one embodiment, output of first sequential unit (FF1) 402 b and firstselection unit 402 c is received by compare unit 402 d. In oneembodiment, 402 d is an XOR (exclusive-OR gate). In other embodiments,other means for comparing signals may be used. In one embodiment, outputof compare unit 402 d is Error signal which is used to generate Rollbacksignal 306. For example, XOR gate (an embodiment of compare unit 402 d)compares write data from a storage unit of queue 402 b and output ofdouble sampled input data 305 c to generate the Error signal on amismatch. In one embodiment, Error signal is sampled by a secondsequential unit (FF2) 402 h to generate Rollback signal 306 for Rollbacklogic 304.

In one embodiment, second EDS 402 comprises a second queue 402 g (e.g.,FIFO, shift-register chain, chain of SRAMs, etc.). In one embodiment,second queue 402 g is coupled to write-pointer logic 402 i and compareunit 402 d. In one embodiment, second queue 402 g is a 1-bit error FIFOwhich logs the Error signal from compare unit 402 d. In one embodiment,the number of storage units in second queue 402 g is the same as thenumber of storage units in first queue 402 a. Such an embodiment allowsthe Error signal to move in “lock step” with the forward datapropagation (i.e., read operation of first queue 402 a). In oneembodiment, output of second queue 402 g is received by logic 402 fwhich validates the output.

In one embodiment, second EDS 402 comprises a second selection unit 402e (e.g., multiplexer 402 e) which is operable to select output of one ofthe storage units of first queue 402 a. In one embodiment, read-pointer(RdPtr) logic 402 j generates the select signal for second selectionunit 402 e causing second selection unit 402 e to generate an output 402k which is the output being read from first queue 402 a. In oneembodiment, logic 402 f (e.g., AND logic gate) performs a logical ANDoperation on 402 a and output of second queue (error queue) to determinewhether the output being read from first queue 402 a is a valid output.While the embodiment shows logic 402 f implemented as an AND logic gate,other logic gates may be used to perform the AND operation (e.g., NANDgate followed by an inverter).

In one embodiment, if it is determined that output 305 d from logic 402f indicates a valid output (i.e., an output with no timing failures),then output 402 k is passed on to a following circuit e.g., anotherdata-path (not shown). In one embodiment, if it is determined thatoutput 305 d from logic 402 f is invalid data (i.e. data generated fromtiming failures) then output 402 k is not passed on to a followingcircuit but is corrected by asking first queue 401 a of first EDS 401 toresend the data.

In one embodiment, Error signal from compare unit 402 d is generated oneclock (CLK) cycle after timing failure event. In such an embodiment,Rollback signal 306 is generated two clock (CLK) cycles after thefailure event, and is routed back to the sending EDS (i.e., first EDS401). In one embodiment, replay logic 304 receives Rollback signal 306and begins the recovery process. In such an embodiment, timing failurein downstream queue (i.e., first queue 402 a of second EDS 402) triggersthe recovery process.

In one embodiment, recovery is accomplished by reading/replaying thefailing data again from the transmitting queue (e.g. first queue 401 aof first EDS 401). In one embodiment, replaying is performed by rollingback the state by two clock (CLK) cycles. Here, the two clock cyclesensure that meta-stability is avoided. However, in other embodiments,other numbers of clock cycles may be used to avoid meta-stabilityissues.

In one embodiment, replay logic 304 comprises a control (Ctrl) logic 403that adjusts the position of read pointer in response to receivingRollback signal 306. In one embodiment, replay logic 304 comprises acircular counter (not shown). In one embodiment, replay logic 304comprises read pointer (Rd Ptr) logic 408 which receives the signal fromcontrol logic 403 to generate read pointer 306 for first queue 401 a offirst EDS 401. In one embodiment, read pointer logic 408 comprises acircular counter (not shown).

In one embodiment, control logic 403 is a generic control logic which isused to update the read pointer for queue 401 a. In one embodiment,control logic 403 includes states of its own which need to be rolledback along with the read pointers when a roll back request (indicated byRollback signal 306) arrives. In one embodiment, Error signal from thecompare unit 402 d is provided, instead of Rollback signal 306 or inaddition to Rollback signal 306, to control logic 403.

In one embodiment, replay logic 304 comprises control logic 404 to storecurrent or present state of read and write pointers. In one embodiment,replay logic 304 comprises control logic 405 which saves the previousread and write pointers. In one embodiment, control logic 404 includesthe latest state for the control logic 403 while control logic 405denotes the prior states for control logic 403. In one embodiment, thenumber of old states retained is typically two. However, in otherembodiments, other numbers (greater or less than two) of older statesmay be retained. In one embodiment, when Rollback signal 306 is receivedby control logic 402, control logic 403 copies the old states fromcontrol logic 405 to present state in control logic 404 and resumesexecution from a previous time stamp.

In one embodiment, replay logic 304 comprises logic 406 to storeprevious state of read pointer. For example, logic 406 includes the readpointer values at an earlier time stamp (e.g., T−1, where ‘T’ is thecurrent time). In one embodiment, replay logic 304 comprises logic 407to store current or present state of read pointer. For example, logic407 includes read pointer value for the current time stamp (e.g., ‘T’).In one embodiment, the number of previous states (or old states)retained by logic 406 is two. In other embodiments, fewer or more thantwo previous states may be retained by logic 406.

In one embodiment, a back-up copy of control state elements (e.g., readand write pointers) of first queue 401 a of first EDS 401 aremaintained. This back-up copy allows restoration of first queue 401 a toa previous state which is two clock cycles ago. In one embodiment, afterthe queue 401 a rolls back to a previous state, the filing transmissionis replayed until there are no timing failures in the second queue 402 gof second EDS 402. In one embodiment, if timing failures continue tooccur despite replaying of data from transmitting queue to receivingqueue then power supply level for various circuits (or all circuits)involved in the first EDS 401, second EDS 402, and data-path 303 israised from its previous level or operational frequency is reduced fromits previous level.

In one embodiment, first and second queues (e.g., 401 a and 402 a) offirst and second EDSs 401 and 402 comprise of positive or negativelatches. The explanation provided here is for positive latches only, buta similar scheme can be implemented with negative latches as well. Theembodiments combine error-detection and recovery circuits with dynamicadaptation to adapt to operating environment (e.g., power supply droops,temperature changes, etc.) to deliver robust silicon (i.e., siliconwithout or substantially zero timing failures).

FIG. 5 illustrates a timing sequence 500, according to one embodiment ofthe disclosure. It is pointed out that those elements of FIG. 5 havingthe same reference numbers (or names) as the elements of any otherfigure can operate or function in any manner similar to that described,but are not limited to such.

During the rising edge of first pulse 501 of clock signal CLK, data 305a is sampled by first queue 401 a of first EDS 401. In this example, atthe falling edge of first pulse 501, incorrect data is written intofirst queue 402 a of second EDS 402. On the next rising edge (of secondpulse 502) of clock signal CLK, Rollback signal 306 is generated. Ifthere is data which is wrongly written into queue 402 a, then Errorsignal is generated during the low-phase for the clock (CLK). On thethird rising edge (of third pulse 503) of clock signal CLK, read pointerfor the source queue (here, queue 401 a) is restored to an older state(e.g., state at T−2, where ‘T’ is the current time).

FIG. 6 is a smart device or a computer system or a SoC (system-on-chip)with queue embedded in parallel with the sampler, according to oneembodiment of the disclosure. It is pointed out that those elements ofFIG. 6 having the same reference numbers (or names) as the elements ofany other figure can operate or function in any manner similar to thatdescribed, but are not limited to such.

FIG. 6 illustrates a block diagram of an embodiment of a mobile devicein which flat surface interface connectors could be used. In oneembodiment, computing device 1600 represents a mobile computing device,such as a computing tablet, a mobile phone or smart-phone, awireless-enabled e-reader, or other wireless mobile device. It will beunderstood that certain components are shown generally, and not allcomponents of such a device are shown in computing device 1600.

In one embodiment, computing device 1600 includes a first processor 1610with EDS 200, according to the embodiments discussed. Other blocks ofthe computing device 1600 may also include EDS 200. The variousembodiments of the present disclosure may also comprise a networkinterface within 1670 such as a wireless interface so that a systemembodiment may be incorporated into a wireless device, for example, cellphone or personal digital assistant.

In one embodiment, processor 1610 can include one or more physicaldevices, such as microprocessors, application processors,microcontrollers, programmable logic devices, or other processing means.The processing operations performed by processor 1610 include theexecution of an operating platform or operating system on whichapplications and/or device functions are executed. The processingoperations include operations related to I/O (input/output) with a humanuser or with other devices, operations related to power management,and/or operations related to connecting the computing device 1600 toanother device. The processing operations may also include operationsrelated to audio I/O and/or display I/O.

In one embodiment, computing device 1600 includes audio subsystem 1620,which represents hardware (e.g., audio hardware and audio circuits) andsoftware (e.g., drivers, codecs) components associated with providingaudio functions to the computing device 1600. Audio functions caninclude speaker and/or headphone output, as well as microphone input.Devices for such functions can be integrated into computing device 1600,or connected to the computing device 1600. In one embodiment, a userinteracts with the computing device 1600 by providing audio commandsthat are received and processed by processor 1610.

Display subsystem 1630 represents hardware (e.g., display devices) andsoftware (e.g., drivers) components that provide a visual and/or tactiledisplay for a user to interact with the computing device 1600. Displaysubsystem 1630 includes display interface 1632, which includes theparticular screen or hardware device used to provide a display to auser. In one embodiment, display interface 1632 includes logic separatefrom processor 1610 to perform at least some processing related to thedisplay. In one embodiment, display subsystem 1630 includes a touchscreen (or touch pad) device that provides both output and input to auser.

I/O controller 1640 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 1640 is operable tomanage hardware that is part of audio subsystem 1620 and/or displaysubsystem 1630. Additionally, I/O controller 1640 illustrates aconnection point for additional devices that connect to computing device1600 through which a user might interact with the system. For example,devices that can be attached to the computing device 1600 might includemicrophone devices, speaker or stereo systems, video systems or otherdisplay devices, keyboard or keypad devices, or other I/O devices foruse with specific applications such as card readers or other devices.

As mentioned above, I/O controller 1640 can interact with audiosubsystem 1620 and/or display subsystem 1630. For example, input througha microphone or other audio device can provide input or commands for oneor more applications or functions of the computing device 1600.Additionally, audio output can be provided instead of, or in addition todisplay output. In another example, if display subsystem 1630 includes atouch screen, the display device also acts as an input device, which canbe at least partially managed by I/O controller 1640. There can also beadditional buttons or switches on the computing device 1600 to provideI/O functions managed by I/O controller 1640.

In one embodiment, I/O controller 1640 manages devices such asaccelerometers, cameras, light sensors or other environmental sensors,or other hardware that can be included in the computing device 1600. Theinput can be part of direct user interaction, as well as providingenvironmental input to the system to influence its operations (such asfiltering for noise, adjusting displays for brightness detection,applying a flash for a camera, or other features).

In one embodiment, computing device 1600 includes power management 1650that manages battery power usage, charging of the battery, and featuresrelated to power saving operation. Memory subsystem 1660 includes memorydevices for storing information in computing device 1600. Memory caninclude nonvolatile (state does not change if power to the memory deviceis interrupted) and/or volatile (state is indeterminate if power to thememory device is interrupted) memory devices. Memory subsystem 1660 canstore application data, user data, music, photos, documents, or otherdata, as well as system data (whether long-term or temporary) related tothe execution of the applications and functions of the computing device1600.

Elements of embodiments are also provided as a machine-readable medium(e.g., memory 1660) for storing the computer-executable instructions(e.g., instructions to implement any other processes discussed herein).The machine-readable medium (e.g., memory 1660) may include, but is notlimited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs,EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM),or other types of machine-readable media suitable for storing electronicor computer-executable instructions. For example, embodiments of thedisclosure may be downloaded as a computer program (e.g., BIOS) whichmay be transferred from a remote computer (e.g., a server) to arequesting computer (e.g., a client) by way of data signals via acommunication link (e.g., a modem or network connection).

Connectivity 1670 includes hardware devices (e.g., wireless and/or wiredconnectors and communication hardware) and software components (e.g.,drivers, protocol stacks) to enable the computing device 1600 tocommunicate with external devices. The computing device 1600 could beseparate devices, such as other computing devices, wireless accesspoints or base stations, as well as peripherals such as headsets,printers, or other devices.

Connectivity 1670 can include multiple different types of connectivity.To generalize, the computing device 1600 is illustrated with cellularconnectivity 1672 and wireless connectivity 1674. Cellular connectivity1672 refers generally to cellular network connectivity provided bywireless carriers, such as provided via GSM (global system for mobilecommunications) or variations or derivatives, CDMA (code divisionmultiple access) or variations or derivatives, TDM (time divisionmultiplexing) or variations or derivatives, or other cellular servicestandards. Wireless connectivity (or wireless interface) 1674 refers towireless connectivity that is not cellular, and can include personalarea networks (such as Bluetooth, Near Field, etc.), local area networks(such as Wi-Fi), and/or wide area networks (such as WiMax), or otherwireless communication.

Peripheral connections 1680 include hardware interfaces and connectors,as well as software components (e.g., drivers, protocol stacks) to makeperipheral connections. It will be understood that the computing device1600 could both be a peripheral device (“to” 1682) to other computingdevices, as well as have peripheral devices (“from” 1684) connected toit. The computing device 1600 commonly has a “docking” connector toconnect to other computing devices for purposes such as managing (e.g.,downloading and/or uploading, changing, synchronizing) content oncomputing device 1600. Additionally, a docking connector can allowcomputing device 1600 to connect to certain peripherals that allow thecomputing device 1600 to control content output, for example, toaudiovisual or other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, the computing device 1600 can make peripheralconnections 1680 via common or standards-based connectors. Common typescan include a Universal Serial Bus (USB) connector (which can includeany of a number of different hardware interfaces), DisplayPort includingMiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI),Firewire, or other types.

Reference in the specification to “an embodiment,” “one embodiment,”“some embodiments,” or “other embodiments” means that a particularfeature, structure, or characteristic described in connection with theembodiments is included in at least some embodiments, but notnecessarily all embodiments. The various appearances of “an embodiment,”“one embodiment,” or “some embodiments” are not necessarily allreferring to the same embodiments. If the specification states acomponent, feature, structure, or characteristic “may,” “might,” or“could” be included, that particular component, feature, structure, orcharacteristic is not required to be included. If the specification orclaim refers to “a” or “an” element, that does not mean there is onlyone of the elements. If the specification or claims refer to “anadditional” element, that does not preclude there being more than one ofthe additional element.

Furthermore, the particular features, structures, functions, orcharacteristics may be combined in any suitable manner in one or moreembodiments. For example, a first embodiment may be combined with asecond embodiment anywhere the particular features, structures,functions, or characteristics associated with the two embodiments arenot mutually exclusive.

While the disclosure has been described in conjunction with specificembodiments thereof, many alternatives, modifications and variations ofsuch embodiments will be apparent to those of ordinary skill in the artin light of the foregoing description. For example, other memoryarchitectures e.g., Dynamic RAM (DRAM) may use the embodimentsdiscussed. The embodiments of the disclosure are intended to embrace allsuch alternatives, modifications, and variations as to fall within thebroad scope of the appended claims.

In addition, well known power/ground connections to integrated circuit(IC) chips and other components may or may not be shown within thepresented figures, for simplicity of illustration and discussion, and soas not to obscure the disclosure. Further, arrangements may be shown inblock diagram form in order to avoid obscuring the disclosure, and alsoin view of the fact that specifics with respect to implementation ofsuch block diagram arrangements are highly dependent upon the platformwithin which the present disclosure is to be implemented (i.e., suchspecifics should be well within purview of one skilled in the art).Where specific details (e.g., circuits) are set forth in order todescribe example embodiments of the disclosure, it should be apparent toone skilled in the art that the disclosure can be practiced without, orwith variation of, these specific details. The description is thus to beregarded as illustrative instead of limiting.

The following examples pertain to further embodiments. Specifics in theexamples may be used anywhere in one or more embodiments. All optionalfeatures of the apparatus described herein may also be implemented withrespect to a method or process.

For example, in one embodiment, an apparatus comprises: a first errordetection sequential (EDS) having a first first-in/first-out (FIFO)queue coupled in parallel to a first sequential unit such that the firstFIFO queue and first sequential unit of the first EDS receive a firstinput; a second EDS having a first FIFO queue coupled in parallel to afirst sequential unit such that the first FIFO queue and firstsequential unit of the second EDS receive a second input; and adata-path logic to receive output of the first EDS and to provide thesecond input to the second EDS.

In one embodiment, the second EDS comprises: a first compare unit toreceive an output from the first sequential unit; and a first selectionunit controllable by a write pointer of a previous cycle, the firstselection unit to receive outputs of each storage unit of the first FIFOqueue, and wherein the first selection unit to generate an output forcomparison by the first compare unit to conditionally generate one ormore error signals. In one embodiment, the second EDS comprises a secondsequential unit to receive output of the first compare unit, the outputof the second sequential unit is coupled to the first EDS. In oneembodiment, the output of the second sequential unit to adjust readpointer of the first EDS.

In one embodiment, the second EDS comprises a second FIFO queue toreceive output of the first compare unit. In one embodiment, the secondEDS comprises a second selection unit to receive the outputs of eachstorage unit of the first FIFO queue, the second selection unitcontrollable by a read pointer. In one embodiment, the second EDScomprises a logic unit to receive output of the second selection unitand output of a storage unit of the second FIFO queue, the output of thestorage unit of the second FIFO queue selected using the read pointer,the logic unit to generate an output of the second EDS.

In one embodiment, the first and second FIFO queues each comprise atleast three storage units. In one embodiment, the first and second FIFOqueues include one of: an SRAM cell; a flip-flop; or a latch. In oneembodiment, the first sequential unit is operable to double sample thefirst input.

In another example, an apparatus comprises: a first sequential unit; afirst queue coupled in parallel to the first sequential unit such thatthe first queue and first sequential unit receive a first input; acompare unit to receive an output from the first sequential unit; and afirst selection unit controllable by a write pointer of a previouscycle, the first selection unit to receive outputs of each storage unitof the first queue, wherein the first selection unit to generate anoutput for comparison by the first compare unit.

In one embodiment, the apparatus further comprises: a second sequentialunit to receive output of the compare unit, the output of the secondsequential unit to generate a rollback signal for adjusting a readpointer for another queue or the first EDS. In one embodiment, theapparatus further comprises a read pointer logic to offset readoperation of the first queue from write operation to the first queue byone or more clock cycles. In one embodiment, the apparatus furthercomprises a second queue to receive output of the compare unit. In oneembodiment, the second queue is a 1-bit first-in/first-out (FIFO) queueto store error history. In one embodiment, the first and second queuesare at least one of: first-in/first-out (FIFO); shift-register; orserial chain of SRAM cells.

In one embodiment, the apparatus further comprises: a second selectionunit to receive the outputs of each storage unit of the first queue, thesecond selection unit controllable by a read pointer. In one embodiment,the apparatus further comprises: a logic unit to receive output of thesecond selection unit and output of a storage unit of the second queue,the output of the storage unit of the second queue selected using theread pointer, the logic unit to generate an output indicating validityof data read from the first queue.

In one embodiment, the first queue comprises at least three storageunits. In one embodiment, the first sequential unit is operable todouble sample the first input. In one embodiment, a system comprises: awireless interface; a memory; and a processor coupled to the memory,wherein the wireless interface to allow the processor to communicatewith another device, wherein the processor includes: a first errordetection sequential (EDS) having a first queue coupled in parallel to afirst sequential unit such that the first queue and first sequentialunit of the first EDS receive a first input; a second EDS having a firstqueue coupled in parallel to a first sequential unit such that the firstqueue and first sequential unit of the second EDS receive a secondinput; and a data-path logic to receive output of the first EDS and toprovide the second input to the second EDS.

In one embodiment, the second EDS comprises: a first compare unit toreceive an output from the first sequential unit; a first selection unitcontrollable by a write pointer of a previous cycle, the first selectionunit to receive outputs of each storage unit of the first queue, andwherein the first selection unit to generate an output for comparison bythe first compare unit; and a second sequential unit to receive outputof the first compare unit, the output of the second sequential unit iscoupled to the first EDS.

An abstract is provided that will allow the reader to ascertain thenature and gist of the technical disclosure. The abstract is submittedwith the understanding that it will not be used to limit the scope ormeaning of the claims. The following claims are hereby incorporated intothe detailed description, with each claim standing on its own as aseparate embodiment.

We claim:
 1. An apparatus comprising: a first sequential unit; a firstqueue coupled in parallel to the first sequential unit such that thefirst queue and first sequential unit receive a first input; a compareunit to receive an output from the first sequential unit; and a firstselection unit controllable by a write pointer of a previous cycle, thefirst selection unit to receive outputs of each storage unit of thefirst queue, wherein the first selection unit to generate an output forcomparison by the first compare unit.
 2. The apparatus of claim 1further comprises: a second sequential unit to receive output of thecompare unit, the output of the second sequential unit to generate arollback signal for adjusting a read pointer for another queue or thefirst EDS.
 3. The apparatus of claim 1 further comprises: a read pointerlogic to offset read operation of the first queue from write operationto the first queue by one or more clock cycles.
 4. The apparatus ofclaim 1 further comprises a second queue to receive output of thecompare unit.
 5. The apparatus of claim 1, wherein the second queue is a1-bit first-in/first-out (FIFO) queue to store error history.
 6. Theapparatus of claim 1, wherein the first and second queues are at leastone of: first-in/first-out (FIFO); shift-register; or serial chain ofSRAM cells.
 7. The apparatus of claim 1 further comprises: a secondselection unit to receive the outputs of each storage unit of the firstqueue, the second selection unit controllable by a read pointer.
 8. Theapparatus of claim 1 further comprises: a logic unit to receive outputof the second selection unit and output of a storage unit of the secondqueue, the output of the storage unit of the second queue selected usingthe read pointer, the logic unit to generate an output indicatingvalidity of data read from the first queue.
 9. The apparatus of claim 1,wherein the first queue comprises at least three storage units.
 10. Theapparatus of claim 1, wherein the first sequential unit is operable todouble sample the first input.